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19-4541; Rev 1; 7/09
Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
General Description
The DS4426 contains four I2C-adjustable current DACs capable of sinking or sourcing current. External resistors set the full-scale range of each output. Each DAC output has 127 sink and 127 source steps that are programmed by the I2C interface. Power-supply tracking functionality is provided for three channels using dedicated control inputs. Once power-supply tracking is accomplished, the current outputs default to zero. Two address pins allow up to four DS4426 devices to exist on the same I2C bus.
Features
Four Current DACs 50A to 200A Adjustable Full-Scale Range 127 Settings Each for Sink and Source Power-Supply Tracking Power-Supply Sequencing Ramp-Up and Ramp-Down Tracking Control Ratiometric Tracking Support +2.7V to +5.5V Operation I2C-Compatible Serial Interface Two Address Input Pins Allow Up to Four Devices on Same I2C Bus Lead-Free, 28-Pin TQFN Package (4mm x 4mm) with Exposed Pad Industrial Temperature Range: -40C to +85C
DS4426
Applications
Power-Supply Adjustment Power-Supply Margining Power-Supply Tracking Adjustable Current Sink or Source
Pin Configuration
PART
THR1 THR2 THR3
Ordering Information
TEMP RANGE -40C to +85C -40C to +85C PIN-PACKAGE 28 TQFN-EP* 28 TQFN-EP* DS4426T+ DS4426T+T&R
TOP VIEW
21 FS1 22 FS2 23 FS3 24 GAIN3 25 GAIN2 26 GAIN1 27 N.C. 28 1 SDA FS0
INN3 16
20
19
18
17
15 14 13 12 INN2 INP2 INN1 INP1 A1 A0 GND
INP3
DNC
+Denotes a lead(Pb)-free/RoHS-compliant package. T&R = Tape and reel. *EP = Exposed pad.
DS4426
11 10
+
2 SCL 3 VCC 4 OUT0 5 OUT1
*EP
9 8
Functional Diagram appears at end of data sheet.
6 OUT2
7 OUT3
THIN QFN (4mm x 4mm)
*EXPOSED PAD.
________________________________________________________________ Maxim Integrated Products
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
ABSOLUTE MAXIMUM RATINGS
Voltage Range on SDA, SCL Relative to GND ......-0.5V to +6.0V Voltage Range on VCC Relative to GND ...............-0.5V to +6.0V Voltage Range on A0, A1, FS[3:0], GAIN[3:1], INN[3:1], INP[3:1], THR[3:1], and OUT[3:0] Relative to GND ......................................-0.5V to (VCC + 0.5V)* *Not to exceed +6.0V.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-55C to +125C Soldering Temperature...........................Refer to the IPC/JEDEC J-STD-020 Specification.
RECOMMENDED OPERATING CONDITIONS
(TA = -40C to +85C.)
PARAMETER Supply Voltage Input Logic 1 (SDA, SCL, A0, A1) Input Logic 0 (SDA, SCL, A0, A1) Full-Scale Resistor Values SYMBOL VCC VIH VIL RFS[3:0] (Note 2) (Note 1) CONDITIONS MIN 2.7 0.7 x VCC -0.3 40 TYP MAX 5.5 VCC + 0.3 0.3 x VCC 160 UNITS V V V k
DC ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Supply Current Input Leakage Current (SDA, SCL) RFS Voltage Reference Voltage Temperature Coefficient Output Leakage Current (SDA) Output-Current Low (SDA) I/O Capacitance IL I OL CI/O VOL = +0.4V VOL = +0.6V -1 3 6 10 SYMBOL ICC I IL VRFS VREF CONDITIONS VCC = +5.5V (Note 3) VCC = +5.5V TA = +25C -1 0.940 0.990 1.24 100 +1 MIN TYP MAX 0.9 +1 1.040 UNITS mA A V V ppm/C A mA pF
DAC OUTPUT CURRENT CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output Current Variation Due to Power-Supply Change Output Current Variation Due to Output-Voltage Change SYMBOL CONDITIONS DC source, V OUT measured at +1.2V DC sink, VOUT measured at +1.2V DC source, VCC = +3.6V DC sink, VCC = +3.6V MIN TYP 0.33 0.33 0.15 0.30 MAX UNITS %/V %/V
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
DAC OUTPUT CURRENT CHARACTERISTICS (continued)
(VCC = +2.7V to +5.5V, TA = -40C to +85C.)
PARAMETER Output Voltage for Sinking Current Output Voltage for Sourcing Current Full-Scale Sink Output Current Full-Scale Source Output Current Output-Current Full-Scale Accuracy Output-Current Temperature Coefficient Output-Current Power-Supply Rejection Ratio Output-Leakage Current at Zero Current Setting Output-Current Differential Linearity Output-Current Integral Linearity I ZERO DNL INL (Note 6) (Note 7) -1 SYMBOL VOUT:SINK (Note 4) CONDITIONS MIN 0.5 0 50 -200 TYP MAX 3.5 VCC 0.75 200 -50 5 130 0.33 +1 0.5 1 UNITS V V A A % ppm/C %/V A LSB LSB
DS4426
VOUT:SOURCE (Note 4) IOUT:SINK (Note 4)
IOUT:SOURCE (Note 4) I OUT:FS I OUT:TC TA = +25C (Note 5)
I2C ELECTRICAL CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C. Timing referenced to VIL(MAX) and VIH(MIN). See Figure 6.)
PARAMETER SCL Clock Frequency Bus Free Time Between STOP and START Conditions Hold Time (Repeated) START Condition Low Period of SCL High Period of SCL Data Hold Time Data Setup Time START Setup Time SDA and SCL Rise Time SDA and SCL Fall Time STOP Setup Time SDA and SCL Capacitive Loading SYMBOL f SCL tBUF tHD:STA tLOW tHIGH tHD:DAT t SU:DAT t SU:STA tR tF t SU:STO CB (Note 9) (Note 9) (Note 9) (Note 8) CONDITIONS MIN 0 1.3 0.6 1.3 0.6 0 100 0.6 20 + 0.1CB 20 + 0.1CB 0.6 400 300 300 0.9 TYP MAX 400 UNITS kHz s s s s s ns s ns ns s pF
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
POWER-SUPPLY TRACKING CHARACTERISTICS
(VCC = +2.7V to +5.5V, TA = -40C to +85C, see Figure 5.)
PARAMETER Input Divider Ratio Output Load Feedback Resistor Ratio Gain Resistor Gain Setting Ratio SYMBOL RDIV RL RF/RB RG RL/RG RL/RG = 2, RL = 5k , VCC = +3.6V, TA = +25C RL/RG = 5, RL = 5k , VCC = +3.6V, TA = +25C 3.8 CONDITIONS RA /RB and RC/RD RL = (RF x RE )/(RF+RE) MIN 0.5 1 0.5 0.8 1.4 2.4 mA/V 6.2 10 1 INP[3:1] and INN[3:1] RL/RG = 1.4; RL = 5k Switch closed, VCC = +3.0V, measured at OUT[3:1], RL = 5k RL/RG = 1.4, R G = 1k , VCC = +3.0V, VFB = +0.8V Switch open 5 5 12.5 0 0 12 1.5 1 600 IBC IOFF VOS tDC VHYS 0.5 1 VCC 1.4 A V MHz V mA mV A A mV s mV TYP MAX 1 20 4.5 10 5 k k UNITS
Power-Supply Tracking Gain
GVI
Power-Supply Tracking Input Bias Current Power-Supply Tracking Input Voltage Unity Gain Bandwidth Output Voltage While Tracking Output Current While Tracking Tracking Accuracy Output Leakage Comparator Input Bias Current Comparator Input Offset Switch Delay Comparator Hysteresis
IB VIN GBW VOUT:TRK I OUT:TRK
Note 1: All voltages are referenced to GND. Current entering the IC is specified positive, and current exiting the IC is negative. Note 2: Input resistors (RFS[3:0]) must be between the specified values to ensure the device meets its accuracy and linearity specifications. Note 3: Supply current specified with all outputs set to zero current setting and with all inputs at VCC or GND. SDA and SCL are connected to VCC. Excludes current through RFS resistors (IRFS). Total current including IRFS is ICC + (2 x IRFS). Note 4: The output-voltage full-scale ranges must be satisfied to ensure the device meets its accuracy and linearity specifications. Only applies to current DAC operation, not power-supply tracking operation. Note 5: Temperature drift excludes drift caused by external resistors. Note 6: Differential linearity is defined as the difference between the expected incremental current increase with respect to position and the actual increase. The expected incremental increase is the full-scale range divided by 127. Note 7: Integral linearity is defined as the difference between the expected value as a function of the setting and the actual value. The expected value is a straight line between the zero and the full-scale values proportional to the setting. Note 8: Timing shown is for fast-mode operation (400kHz). This device is also backward-compatible with I2C standard-mode timing. Note 9: CB--Total capacitance of one bus line in pF.
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
Typical Operating Characteristics
(TA = +25C, unless otherwise noted.)
DS4426
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS4426 toc01
SUPPLY CURRENT vs. TEMPERATURE
DS4426 toc02
VOLTCO (SOURCE)
40k LOAD ON FS[3:0]. VCC = +5.5V -175 IOUT (A)
DS4426 toc03
600 575 SUPPLY CURRENT (A) 550 525 500 475 450 425 400
SDA = SCL = THR[3:1] = VCC GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN INP[3:1] = INN[3:1] = GND
600 575 SUPPLY CURRENT (A) 550 525 500 475 VCC = +2.7V 450 425 400 SDA = SCL = THR[3:1] = VCC GAIN[3:1] = FS[3:0] = OUT[3:0] = OPEN INP[3:1] = INN[3:1] = GND -40 -20 0 20 40 60 80 VCC = +5.5V VCC = +3.3V
-150
-200
-225 SDA = SCL = THR[3:1] = VCC GAIN[3:1] = OPEN INP[3:1] = INN[3:1] = GND -250 0 1 2 VOUT (V) 3 4 5
2.5
3.0
3.5
4.0
4.5
5.0
5.5
SUPPLY VOLTAGE (V)
TEMPERATURE (C)
VOLTCO (SINK)
DS4426 toc04
TEMPERATURE COEFFICIENT vs. SETTING (SOURCE)
DS4426 toc05
TEMPERATURE COEFFICIENT vs. SETTING (SINK)
TEMPERATURE COEFFICIENT (C/ppm) 550 450 350 250 150 50 -50 -150 -250 0 25 50 75 100 125 +25C TO +85C +25C TO -40C RANGE FOR THE 50A TO 200A CURRENT SINK RANGE
DS4426 toc06
250 40k LOAD ON FS[3:0]. VCC = +5.5V 225 IOUT (A)
300 TEMPERATURE COEFFICIENT (C/ppm) 250 200 150 +25C TO -40C 100 50 0 -50 +25C TO +85C 0 25 50 75 100 125 RANGE FOR THE 50A TO 200A CURRENT SOURCE RANGE
650
200
175 SDA = SCL = THR[3:1] = VCC GAIN[3:1] = OPEN INP[3:1] = INN[3:1] = GND 150 0 0.5 1.0 1.5 2.0 VOUT (V) 2.5 3.0 3.5 4.0
SETTING (DEC)
SETTING (DEC)
INTEGRAL LINEARITY
DS4426 toc07
DIFFERENTIAL LINEARITY
0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 RANGE FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE
DS4426 toc08
1.0 0.8 0.6 0.4 INL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 RANGE FOR THE 50A TO 200A CURRENT SOURCE AND SINK RANGE
1.0
125
0
25
50
75
100
125
SETTING (DEC)
SETTING (DEC)
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
Pin Description
PIN 1 2 3 4 5, 6, 7 8 9 10 11, 13, 15 12, 14, 16 17, 19, 20 18 21-24 25, 26, 27 28 -- NAME SDA SCL VCC OUT0 OUT1, OUT2, OUT3 GND A0 A1 INP1, INP2, INP3 INN1, INN2, INN3 THR3, THR2, THR1 DNC FS0, FS1, FS2, FS3 GAIN3, GAIN2, GAIN1 N.C. EP Serial Clock Input. I2C clock input. Voltage Supply Current DAC Output Current DAC and Tracking Control Output Ground I2C Address Input 0 I2C Address Input 1 Power-Supply Tracking Positive Input Power-Supply Tracking Negative Input Threshold Input. Comparator input used to set threshold for tracking enable/disable based on VREF/2. Do Not Connect Full-Scale Calibration Input. A resistor-to-ground on this input determines fullscale output current on the associated output. Gain Adjustment Pin. Connect a resistor between this pin and VCC. No Connection Exposed Pad. No connection. FUNCTION Serial Data Input/Output. I2C data pin.
Detailed Description
The DS4426 contains four I 2 C-adjustable current sources that are each capable of sinking and sourcing current. Three of the current outputs (OUT[3:1]) also have power-supply tracking circuitry that allows additional current to be sourced during power-up.
To calculate the output-current value (IOUT) based on the corresponding DAC value (see Table 2 for corresponding memory addresses), use the following equation: IOUT = DACValue(dec) x IFS 127
Adjustable Current DACs
Each output (OUT[3:0]) has 127 sink and 127 source settings that are programmed through the I2C interface. The full-scale current ranges (and corresponding step sizes) of the outputs are determined by external resistors connected to the corresponding FS pins (see Figure 1). The formula to determine the external resistor values (RFS) for each output is given by: R FS = VRFS x 127 16 x IFS
where IFS is the desired full-scale current value, VRFS is the RFS voltage (see the DC Electrical Characteristics table), and RFS is the external resistor value.
On power-up, the DS4426 current DAC outputs are set to zero current. This is done to prevent the device from sinking or sourcing an incorrect current before the system host controller has a chance to modify its setting. Note, however, that if power-supply tracking is enabled (see the Power-Supply Tracking Circuit section), then the DS4426 can still source current at power-up. When used in adjustable power-supply applications (see Figure 8), the DS4426 does not affect the initial power-up voltage of the supply because it defaults to providing zero output current on power-up unless power-supply tracking is enabled. As it sources or sinks current into the feedback voltage node, it changes the amount of output voltage required by the regulator to reach its steady-state operating point.
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
I2C CONTROL MSB LSB TRACKING OUT[3:1] ONLY
SOURCE OR SINK MODE
CURRENT DAC[3:0]
127 POSITIONS EACH FOR SOURCE AND SINK MODE
Using the external resistors RFS[3:0] to set the outputcurrent range, the DS4426 provides some flexibility for adjusting the impedances of the feedback network or the range over which the power supply can be controlled or margined. As a source for biasing instrumentation or other circuits, the DS4426 provides a simple and inexpensive current source with an I2C interface for control. The adjustable, full-scale range allows the application to get the most out of its 7-bit sink or source resolution.
DS4426
FS[3:0] RFS[3:0]
OUT[3:0]
Power-Supply Tracking Circuit
By making use of the power-supply tracking circuitry, the DS4426 has the ability to source current on powerup. This current is additive with the current DAC source/sink currents and is determined by the value of the gain resistor, RG, and the supply voltage, VCC. This current is controlled by the voltages presented to the corresponding INP and INN pins, and the voltages presented to the corresponding threshold (THR) pins.
VCC
Figure 1. Current DAC Detail
Maximum Source Current
RG GAIN INP + GVI INN OUT SLAVE FEEDBACK NODE
The maximum current the DS4426 can source at power-up using the power-supply tracking circuitry depends on the value of the supply voltage, VCC, and the gain resistor, RG, connected from the corresponding GAIN pin to VCC. The maximum current (IMAX) that can be sourced to the corresponding OUT pin can be estimated using the following equation: IMAX
SHUTDOWN DAC
( VCC - VOUT )
RG
Figure 2. Gain Stage
I IMAX AT VCC = +5.0V
The power-supply tracking circuit can be estimated with Figure 2.
Inputs for Power-Supply Tracking: INP and INN
Each pair of power-supply tracking inputs, INP and INN, determines if and how much of the IMAX current is sourced when the power-supply tracking circuit is enabled. When the difference between the voltage presented to INP (V INP ) and INN (V INN ) is more than approximately +0.3V, then the maximum source current, as determined by the value IMAX, is sourced into the OUT pin connection. When the difference between VINP and VINN is less than approximately -0.2V, then no current is sourced into the corresponding OUT pin. The change in current from no current to IMAX can be estimated by the power-supply tracking gain, GVI (see the Power-Supply Tracking Characteristics table). Figure 3 shows the typical current behavior of the power-supply tracking circuit with respect to the voltage difference seen at the INP and INN inputs.
7
GVI
-0.2
+0.3
V (VINP - VINN)
Figure 3. INP and INN Differential Inputs
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
V
VMASTER
VSLAVE VTHRESHOLD
DS4426 TRACKING DISABLED
GAIN ERROR TRACKING RANGE: DS4426 OVERRIDES SLAVE'S FEEDBACK LOOP
t
Figure 4. Enabling Power-Supply Tracking Using the THR Input
THR Inputs for Enabling Power-Supply Tracking
Comparators are used to individually enable/disable power-supply tracking based on the voltage presented to the corresponding THR pin relative to a fixed internal reference (VREF/2 = +0.62V). Figure 4 shows a typical startup and shutdown plot based on the voltage presented to the THR pin. Tracking can be disabled by connecting the corresponding THR pin to a voltage greater than VREF/2. Below this threshold, the tracking circuit is active.
Loop Bandwidth Consideration
Power-supply tracking is used to override each slave DC-DC's feedback loop during power-up and powerdown. Power-supply tracking is capable of slewing at a much faster rate than most DC-DC converters. Care must be exercised when selecting the loop bandwidth of the master DC-DC, slave DC-DC, and power-supply tracking control loop such that oscillations and overshoot are minimized. While the slave DC-DC supplies are tracking the master DC-DC supply, there are three time constants of concern: 1) Master BW. The master DC-DC control loop bandwidth, power-up ramp rate, and power-down ramp rate. 2) Slave BW. The slave DC-DC supplies control loop bandwidths. 3) Tracking BW. The DS4426 tracking circuit bandwidth. To ensure stable operation and minimize peaking, the bandwidths should follow the following rule: Master BW and Slave BW < (Tracking BW/10)
Power-Supply Tracking in DC-DC Power Applications
The DS4426 provides several options for power-supply tracking control of DC-DC power supplies. In many cases, it is desirable to prevent certain DC-DC supplies from exceeding the voltage of other supplies. This is often the case with the voltages applied to a digital core and I/O. Each DS4426 supports one master with three slave DC-DCs. See Figure 5 for more information.
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
5.0V VCC 0.1F 10k I 2C 10k 10k SDA SCL A0 A1 VREF REF 1.24V x3 INP[3:1] 5.0V RB[3:1] RG[3:1] RA[3:1] GAIN[3:1] VREF/2 DS4426 INN[3:1] VOUT SLAVE DC-DC CONVERTER COMP THR[3:1] FB RE[3:1] RF[3:1] OUT[3:1] VOUT MASTER DC-DC CONVERTER I2C CONTROL INTERFACE FS0 OUT0 FS[3:1] RFS[3:1] RFS0 FB RE0 RF0 VCC
10k
RTHR[3:1] RD[3:1] RC[3:1]
Figure 5. Typical DC-DC Power-Supply Tracking Application
Ratiometric Tracking
The DS4426 can maintain a defined ratio between a slave voltage and the master voltage where: KSM = VSLAVE/VMASTER. In Figure 5, this ratio is given by the following: KSM = [RB[3:1]/(RA[3:1] + RB[3:1])]/[RD[3:1]/(RC[3:1] + RD[3:1])]. Nonratiometric tracking is the special case where KSM = 1.
Power-Supply Tracking Loop Gain Stability
Slave DC-DC output tracking is controlled by the DS4426 sourcing current into the slave DC-DC's feedback loop. This changes the stability of the loop during tracking. The amount of gain used can be adjusted by
changing the ratio of R L /R G . If oscillations occur, increasing RG reduces gain and increases the system's phase margin. If the slave DC-DC has a compensation pin, the RC network connected to this pin can also be adjusted to improve phase margin. This pin is often labeled COMP or ITH. A larger compensation time constant (increased R and/or increased C) often increases the stability of the system during tracking; however, this also modifies the DC-DC's transient response. In order to prevent modification of the slave DC-DC's transient response after power-supply tracking is complete, RG should first be modified before adjusting the compensation network. The higher the gain, the less the gain error. Reducing the gain increases the gain error during tracking. See Figure 4 for more information.
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
Table 1. Slave Addresses
A1 GND GND VCC VCC A0 GND VCC GND VCC SLAVE ADDRESS (HEX) 90h 92h 94h 96h
Table 2. Memory Addresses
MEMORY ADDRESS (HEX) F8h F9h FAh FBh CURRENT SOURCE OUT0 OUT1 OUT2 OUT3
Inputs for Tracking in DC-DC Power Applications
When enabling/disabling the power-supply tracking, a resistor-divider connected to the THR input sets the disable threshold (see VTHRESHOLD in Figure 4). The top of the resistor-divider must be connected to the master DC-DC voltage for correct operation. Below this threshold, the tracking circuit is active.
Memory Organization
The DS4426's current sources are controlled by writing to memory addresses listed in Table 2. The format of each of the output control registers is given by:
BIT 7 (MSB) S BIT 6 D6 BIT 5 D5 BIT 4 D4 BIT 3 D3 BIT 2 D2 BIT 1 D1 BIT 0 (LSB) D0
Power-Supply Sequencing
The DS4426 can be used to perform power-supply sequencing. This is a subset of power-supply tracking with modifications to the external resistor network. The basic concept is that the DS4426 sources maximum current into the slave power supply's feedback node until a voltage in the system has risen above a specific voltage level. By sourcing the maximum current into the feedback node, the power supply's output is held off. Maximum sourcing current is achieved with two steps: 1) Apply the maximum allowed input voltage across INP and INN. Connect INP to VCC - 1.4V using a voltage-divider to ground. Connect INN to ground. 2) Set the gain to the maximum allowed (RL/RG = 5). The slave power supply is allowed to turn on once the voltage on THR is greater than VREF/2. Use a resistordivider connected to the rising system voltage to scale the trip point to VREF/2.
where:
BIT NAME Sign Bit DESCRIPTION Determines if DAC sources or sinks current. For sink, S = 0. For source, S = 1. 7-bit data word controlling DAC output. Setting 0000000b outputs zero current regardless of the state of the sign bit. POWER-ON DEFAULT 0b
S
DX
Data
0000000b
I2C Slave Address
The DS4426 responds to one of four I2C slave addresses determined by the state of the input on the two address inputs. The two input states are connected to VCC or connected to ground.
For example: RFS0 = 80k and register 0xF8h is written to a value of 0xAAh. Use the following formula to calculate the output current: IFS = (1.0V/80k) x (127/16) = 99.22A The MSB of the output register is 1, so the output is sourcing the value corresponding to position 2Ah (42 decimal). The magnitude of the output current is equal to the following: 99.22A x (42/127) = 32.8125A
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
I2C Serial Interface Description
I2C Definitions The following terminology is commonly used to describe I2C data transfers: I 2 C Slave Address: The slave address of the DS4426 is determined by the state of the A0 and A1 pins (see Table 1). Master Device: The master device controls the slave devices on the bus. The master device generates SCL clock pulses and START and STOP conditions. Slave Devices: Slave devices send and receive data at the master's request. Bus Idle or Not Busy: Time between STOP and START conditions when both SDA and SCL are inactive and in their logic-high states. When the bus is idle it often initiates a low-power mode for slave devices. START Condition: A START condition is generated by the master to initiate a new data transfer with a slave. Transitioning SDA from high to low while SCL remains high generates a START condition. See Figure 3 for applicable timing. STOP Condition: A STOP condition is generated by the master to end a data transfer with a slave. Transitioning SDA from low to high while SCL remains high generates a STOP condition. See Figure 3 for applicable timing. Repeated START Condition: The master can use a repeated START condition at the end of one data transfer to indicate that it will immediately initiate a new data transfer following the current one. Repeated STARTs are commonly used during read operations to identify a specific memory address to begin a data transfer. A repeated START condition is issued identically to a normal START condition. See Figure 6 for applicable timing.
Bit Write: Transitions of SDA must occur during the low state of SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL, plus the setup-and-hold time requirements (Figure 6). Data is shifted into the device during the rising edge of the SCL. Bit Read: At the end of a write operation, the master must release the SDA bus line for the proper amount of setup time (Figure 6) before the next rising edge of SCL during a bit read. The device shifts out each bit of data on SDA at the falling edge of the previous SCL pulse, and the data bit is valid at the rising edge of the current SCL pulse. Remember that the master generates all SCL clock pulses, including when it is reading bits from the slave. Acknowledgement (ACK and NACK): An Acknowledgement (ACK) or Not Acknowledge (NACK) is always the ninth bit transmitted during a byte transfer. The device receiving data (the master during a read or the slave during a write operation) performs an ACK by transmitting a zero during the ninth bit. A device performs a NACK by transmitting a 1 during the ninth bit. Timing for the ACK and NACK is identical to all other bit writes (Figure 6). An ACK is the acknowledgment that the device is properly receiving data. A NACK is used to terminate a read sequence or as an indication that the device is not receiving data. Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most significant bit first) plus a 1-bit acknowledgement from the slave to the master. The 8 bits transmitted by the master are done according to the bit-write definition, and the acknowledgement is read using the bit-read definition. Byte Read: A byte read is an 8-bit information transfer from the slave to the master plus a 1-bit ACK or NACK from the master to the slave. The 8 bits of information that are transferred (most significant bit first) from the slave to the master are read by the master using the bit-read definition, and the master transmits an ACK using the bit-write definition to receive additional data bytes. The master must NACK the last byte read to terminate communication so the slave returns control of SDA to the master. Slave Address Byte: Each slave on the I2C bus responds to a slave address byte sent immediately following a START condition. The slave address byte contains the slave address in the most significant 7 bits and the R/W bit in the least significant bit. The DS4426's slave address is determined by the state of the A0 and A1 pins (see Table 1). When the R/W bit is 0 (such as in 90h), the master is indicating it will write data to the slave. If R/W = 1 (91h in this case), the master is indicating it wants to read from the slave. If an incorrect slave address is written, the DS4426 assumes the master is communicating with another I2C device and ignores the communication until the next START condition is sent. Memory Address: During an I2C write operation, the master must transmit a memory address to identify the memory location where the slave is to store the data. The memory address is always the second byte transmitted during a write operation following the slave address byte.
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DS4426
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
SDA tBUF tF tLOW SCL tHD:STA tSP
tHIGH tHD:STA tR tHD:DAT STOP START tSU:DAT REPEATED START
tSU:STA
tSU:STO
NOTE: TIMING IS REFERENCED TO VIL(MAX) AND VIH(MIN).
Figure 6. I2C Timing Diagram
TYPICAL I2C WRITE TRANSACTION MSB START 1 0 0 1 0 A1 A0 LSB R/W SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK MSB b7 b6 b5 b4 b3 b2 b1 LSB b0 SLAVE ACK STOP
SLAVE ADDRESS*
READ/ WRITE
REGISTER/MEMORY ADDRESS
DATA
EXAMPLE I2C TRANSACTIONS (WHEN A0 AND A1 ARE GROUNDED) 90h A) SINGLE-BYTE WRITE -WRITE REGISTER F9h TO 00h START 10010000 F9h SLAVE 11111 001 ACK
SLAVE SLAVE 00000000 ACK ACK 91h REPEATED START
STOP
90h B) SINGLE-BYTE READ -READ REGISTER F8h START 10010000
F8h SLAVE SLAVE 11111 000 ACK ACK
DATA SLAVE ACK MASTER NACK STOP
10010 001
*THE SLAVE ADDRESS IS DETERMINED BY ADDRESS PINS A0 AND A1.
Figure 7. I2C Communication Examples
I2C Communication
Writing to a Slave: The master must generate a START condition, write the slave address byte (R/W = 0), write the memory address, write the byte of data, and generate a STOP condition. Remember that the master must read the slave's acknowledgement during all byte-write operations.
Reading from a Slave: To read from the slave, the master generates a START condition, writes the slave address byte with R/W = 1, reads the data byte with a NACK to indicate the end of the transfer, and generates a STOP condition.
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
Applications Information
Example Calculations for an Adjustable Power Supply
In this example, the circuit shown in Figure 8 is used to margin a +2.0V supply by 20%. The margined power supply has a DC-DC converter output voltage, VOUT, of +2.0V and a DC-DC converter feedback voltage, VFB, of +0.8V. To determine the relationship of R0A and R0B, start with the equation: R 0B VFB = x VOUT R 0 A + R 0B Substituting VFB = +0.8V and VOUT = +2.0V, the relationship between R0A and R0B is determined to be: R0A = 1.5 x R0B IOUT0 is chosen to be 100A (midrange source/sink current for the DS4426). Summing the currents into the feedback node, we have the following: IOUT0 = IR0B - IR0A where: IR0B = and IR0 A = VOUT - VFB R 0A VFB R 0B
DS4426
To create a 20% margin in the supply voltage, the value of V OUT is set to +2.4V. With these values in place, R 0B is calculated to be 2.67k, and R 0A is
VCC
VOUT = 2.0V*
4.7k
4.7k SDA SCL
VCC DC-DC CONVERTER DS4426 GND OUT0
OUT IR0A FB IR0B R0B = 2.67k R0A = 4k VFB = 0.8V*
FS0 IOUT0 RFS0 = 80k
*VOUT AND VFB VALUES ARE DETERMINED BY THE DC-DC CONVERTER AND SHOULD NOT BE CONFUSED WITH VOUT AND VREF OF THE DS4426.
Figure 8. Example Typical Application Circuit
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13
Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking DS4426
Functional Diagram
VCC VCC SDA SCL A0 A1 VREF REF 1.24V INP1 OUT1 INN1 GAIN1 VREF/2 I2C CONTROL INTERFACE
calculated to be 4.00k. The current DAC in this configuration allows the output voltage to be moved linearly from +1.6V to +2.4V using 127 settings. This corresponds to a resolution of 6.3mV/step.
VCC Decoupling
To achieve the best results when using the DS4426, decouple the power supply with a 0.01F (or 0.1F) capacitor. Use a high-quality, ceramic, surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance. Ceramic capacitors tend to have adequate high-frequency response for decoupling applications.
FS0 OUT0 FS1
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 28 TQFN PACKAGE CODE T2844+1 DOCUMENT NO. 21-0139
THR1 INP2
FS2 OUT2
INN2 GAIN2 VREF/2
THR2 INP3
FS3 OUT3
INN3 GAIN3 VREF/2
DS4426 THR3 GND
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Quad-Channel, I2C-Margining IDACs with Three Channels of Power-Supply Tracking
Revision History
REVISION NUMBER 0 1 REVISION DATE 4/08 7/09 Initial release. Added OUT[3:0] to the Absolute Maximum Ratings for the following condition: Voltage Range on A0, A1, FS[3:0], GAIN[3:1], INN[3:1], INP[3:1], and THR[3:1]. DESCRIPTION PAGES CHANGED -- 2
DS4426
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 15
(c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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